Interconnecting synchronous circuits communicating on a common synchronous bus will in cases where more than one transceiver for each PCB is necessary involve the use of buffers to avoid signal degradation and ringing on the bus.
For example, the lower layer of communication networks like the connectivity layer in a core network of a cellular environment could be seen as a layer of distributed resources for managing data flows. Switches and multiplexers are some of the main components for this purpose. In complex communication networks managing data of different formats and varying data rates, it is of great importance to keep signal degradation and bit errors at a minimum.
Conventionally, the switches comprise a number of serial inputs and outputs. The data stream of one input may be directed in its entirety to a certain output line, or it may consist of a mixture of time division multiplexed data frames that are to be distributed to several outputs. The different lines may be running various interfaces e.g. E1, E2, E3 and STM-1.
The switching takes place on a TDM-bus system comprising a data bus (DATA) (usually 8 bits) and a data clock (TDM CLK). The time domain is divided into frames where each frame has a fixed duration (usually 125 μs), the start of each frame is indicated with a frame synchronization signal (FSYNC). The frames are divided into a fixed number of timeslots identified by local timeslot counters. In each timeslot, data may be transmitted from a transmitter to a receiver by using time division multiplexing (TDM).
Several transmitters and receivers are able to communicate with each other over the TDM bus when every local timeslot counter is synchronised to FSYNC. FIG. 1 shows how the BUS transceivers typically are connected to a backplane TDM bus. EN(1 . . . N) are timeslot enable signals enabling the timeslots out on the TDM bus.
The architecture indicated in the figure above, i.e. a is system with a large number of loads, may have problems related to degradation of received signals. The more loads a bus is subjected to, the more signal attenuation will occur.
Another drawback causing signal degradation as a result of two or more transceivers on one circuit board connected to the same TDM bus connector is the increase of stub lengths. The multi connection will cause longer stub lengths from the transceiver to the TDM bus because of the physical dimensions of the transceiver IC packages. Long stub lengths may lead to poor bus terminations that in turn may cause reflections and signal attenuation to occur, both of which may increase the bit error rate and retransmission frequency and reduce the data quality.
Another way of solving the busload problem is to have a tree structure of buffers, i.e. coupling together pairs of loads by passive buffers and, in the case of more than two loads, coupling the output of the buffers by additional buffers until only one load for connecting the TDM bus remains. However, this will introduce time delays that are not acceptable in most applications. Only delays that are multiples of whole frames are normally accepted for the total delay from the local TDM bus out on the backplane TDM bus and back on the local TDM bus.